Literature: Stratix Device Handbook
The Stratix™ Device Handbook is comprised of three volumes. Volume 1 is the Stratix FPGA family data sheet; Volume 2 contains detailed information on how to use Stratix features; and Volume 3 is comprised of device pin tables and PCB layout guidelines. To view all three volumes, click the link below.
Volume 1 (ver 2.3, Jan 2004, 1,766 KB) | View
Section I. Stratix Device Family Data Sheet (1,636 KB) | View
- Chapter 1. Introduction (ver 2.2, Jan 2004, 87 KB)
- Chapter 2. Stratix Architecture (ver 2.2, Nov 2003, 1,009 KB)
- Chapter 3. Configuration & Testing (ver 1, Apr 2003, 154 KB)
- Chapter 4. DC & Switching Characteristics (ver 2.2, Nov 2003, 438 KB)
- Chapter 5. Reference & Ordering Information (ver 2, Jul 2003, 43 KB)
Volume 2 (ver 2.2, Nov 2003, 6,400 KB) | View
Section I. Clock Management (1,951 KB) | View
Section II. Memory (958 KB) | View
Section III. I/O Standards (1,347 KB) | View
Section IV. Digital Signal Processing (DSP) (970 KB) | View
Section V. IP & Design Considerations (2,182 KB) | View
- Chapter 8. Double Data Rate I/O Signaling in Stratix & Stratix GX Devices (ver 2.1, Nov 2003, 1,000 KB)
(Replaces AN 212) - Chapter 9. Implementing Multipliers in Stratix, Stratix GX & Cyclone Devices (ver 1.0, Oct 2003, 455 KB)
(Replaces AN 306) - Chapter 10. Implementing 10-Gigabit Ethernet Using Stratix Devices (ver 1.1, Nov 2003, 195 KB)
(Replaces AN 220) - Chapter 11. Implementing SFI-4 in Stratix Devices (ver 1, Apr 2003, 156 KB)
(Replaces AN 219) - Chapter 12. Transitioning APEX Designs to Stratix Devices (ver 1.2, Nov 2003, 272 KB)
(Replaces AN 206)
Section VI. Configuration & Remote System Upgrades (996 KB) | View
Volume 3 (ver 3.0, Feb 2004, 3,600 KB) | View
Section I. Device Pin Information (2,917 KB) | View
- Chapter 1. Stratix EP1S10 Device Pin Information (ver 3.0, Feb 2004, 409 KB)
- Chapter 2. Stratix EP1S20 Device Pin Information (ver 3.0, Feb 2004, 385 KB)
- Chapter 3. Stratix EP1S25 Device Pin Information (ver 3.0, Feb 2004, 408 KB)
- Chapter 4. Stratix EP1S30 Device Pin Information (ver 3.0, Feb 2004, 434 KB)
- Chapter 5. Stratix EP1S40 Device Pin Information (ver 3.0, Feb 2004, 570 KB)
- Chapter 6. Stratix EP1S60 Device Pin Information (ver 3.0, Feb 2004, 525 KB)
- Chapter 7. Stratix EP1S80 Device Pin Information (ver 3.0, Feb 2004, 504 KB)
Section II. PCB Layout Guidelines (693 KB) | View
Related Documentation
Data Sheets
Application Notes
- AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices (ver 1.0, Mar 2004, 165 KB)
- AN 315: Guidelines for Designing High-Speed FPGA PCBs (ver 1.1, Feb 2004, 1,390 KB)
- AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices (ver 1.0, Jan 2004, 273 KB)
- AN 247: Stratix GX to Mercury Interoperability (ver 1.2, Jan 2004, 81 KB)
- AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices (ver 1.0, Nov 2003, 1,425 KB)
- AN 306: Techniques for Implementing Multipliers in Stratix, Stratix GX & Cyclone Devices (ver 1.0, Aug 2003, 391 KB)
- AN 311: ASIC-to-FPGA Design Methodology & Guidelines (ver 1.0, Jul 2003, 1,098 KB)
- AN 307: Altera Design Flow for Xilinx Users (ver 2.0, Jul 2003, 972 KB)
- AN 227: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices (ver 1.0, May 2003, 455 KB)
- AN 228: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices (ver 1.0, May 2003, 632 KB)
- AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (ver 1.0, Jan 2003, 358 KB)
Example 1: Shift Register in LEs ( 276 KB)
Example 2: altpll_reconfig Design with the MIF ( 181 KB)
Example 3: altpll_reconfig Design ( 181 KB) - AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices (ver 1.1, Jan 2003, 176 KB)
- AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs (ver 2.0, Nov 2002, 143 KB)
- AN 207: TriMatrix Memory Selection Using the Quartus II Software (ver 2.1, Nov 2002, 323 KB)
- AN 249: Implementing 10 Gigabit Ethernet XAUI in Stratix GX Devices (ver 1.0, Nov 2002, 406 KB)
- AN 224: High-Speed Board Layout Guidelines (ver 1.0, Nov 2002, 895 KB)
White Papers
- Basic Principles of Signal Integrity (ver 1.1, Feb 2004, 103 KB)
- Implementing a Queue Manager in Traffic Management Systems White Paper (ver 1.1, Feb 2004, 124 KB)
- The Need for Dynamic Phase Alignment in High-Speed FPGAs (ver 1.1, Feb 2004, 70 KB)
- Using Parity to Detect Memory Errors in Stratix Devices White Paper (ver 1.1, Feb 2004, 99 KB)
- Altera Hot-Socketing & Power-Sequencing Advantages White Paper (ver 1.2, Feb 2004, 79 KB)
- The Benefits of Altera’s High-Speed DDR SDRAM Memory Interface Solution White Paper (ver 1.0, Oct 2003, 361 KB)
- Selecting the Correct High Speed Transceiver Solution White Paper (ver 1.0, Sep 2003, 1,764 KB)
- Using Pre-Emphasis and Equalization with Stratix GX White Paper (ver 1.0, Sep 2003, 1,897 KB)
- Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices White Paper (ver 1.0, Aug 2003, 466 KB)
- Using Stratix GX Devices for SONET/SDH Backplanes (ver 1.0, May 2003, 163 KB)
- An
Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices (ver 1.1, May 2003, 116 KB)
- Advantages of the Embedded DPA Circuitry in Stratix GX Devices (ver 1.0, Apr 2003, 303 KB)
- The Truth About Die Size: Comparing Stratix & Virtex-II Pro FPGAs (ver 1.0, Feb 2003, 225 KB)
- Traffic Management in Stratix GX Devices (ver 1.0, Dec 2002, 69 KB)
- Stratix GX in Storage Applications (ver 1.0, Nov 2002, 80 KB)
- Stratix GX in Switch Fabric Systems (ver 1.0, Nov 2002, 222 KB)
- The Evolution of High Speed Transceiver Technology (ver 1.0, Nov 2002, 438 KB)
- Using Stratix GX in HDTV Video Production Applications White Paper (ver 1.0, Nov 2002, 118 KB)
Brochures
Selector Guides
Errata Sheets
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